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Fallout List

port maintainer build environment category date urls
math/lcalc [email protected] main-armv7-default build 2024-11-05 00:57 log report port detail FreshPorts
devel/py-pysimdjson@py311 [email protected] main-armv7-default build 2024-11-04 03:46 log report port detail FreshPorts
lang/gnat13 [email protected] main-armv7-default fetch 2024-11-04 00:07 log report port detail FreshPorts
math/lcalc [email protected] main-amd64-default build 2024-11-03 13:19 log report port detail FreshPorts
math/flexiblas [email protected] main-armv7-default build 2024-11-03 12:50 log report port detail FreshPorts
math/lcalc [email protected] main-i386-default build 2024-11-03 04:40 log report port detail FreshPorts
devel/py-pysimdjson@py311 [email protected] main-amd64-default build 2024-11-03 03:03 log report port detail FreshPorts
math/ntpoly [email protected] 133releng-armv7-default configure 2024-11-02 22:42 log report port detail FreshPorts
devel/py-pysimdjson@py311 [email protected] main-i386-default build 2024-11-02 21:07 log report port detail FreshPorts
lang/gnat13 [email protected] 133releng-armv7-default fetch 2024-11-02 16:57 log report port detail FreshPorts
math/sprng [email protected] 133releng-armv7-default build 2024-11-02 13:20 log report port detail FreshPorts
math/flexiblas [email protected] 133releng-armv7-default build 2024-11-02 13:20 log report port detail FreshPorts
devel/R-cran-rJava [email protected] main-armv7-default stage 2024-11-02 06:58 log report port detail FreshPorts
devel/R-cran-rJava [email protected] 133releng-armv7-default stage 2024-11-02 04:14 log report port detail FreshPorts
math/libdivide [email protected] main-amd64-default build 2024-11-02 04:09 log report port detail FreshPorts
math/libdivide [email protected] main-i386-default build 2024-11-02 03:49 log report port detail FreshPorts
math/libdivide [email protected] main-armv7-default build 2024-11-02 01:58 log report port detail FreshPorts
lang/gnat12 [email protected] 133releng-armv7-default fetch 2024-11-02 01:46 log report port detail FreshPorts
math/lcalc [email protected] main-amd64-default build 2024-11-01 20:26 log report port detail FreshPorts
math/lcalc [email protected] main-i386-default build 2024-11-01 14:03 log report port detail FreshPorts
lang/gnat12 [email protected] main-armv7-default fetch 2024-11-01 12:35 log report port detail FreshPorts
devel/py-pysimdjson@py311 [email protected] main-amd64-default build 2024-11-01 11:28 log report port detail FreshPorts
devel/py-pysimdjson@py311 [email protected] main-i386-default build 2024-11-01 05:09 log report port detail FreshPorts
math/lcalc [email protected] main-arm64-default build 2024-10-31 20:12 log report port detail FreshPorts
math/libdivide [email protected] main-amd64-default build 2024-10-31 03:59 log report port detail FreshPorts
math/libdivide [email protected] main-i386-default build 2024-10-31 03:23 log report port detail FreshPorts
math/lcalc [email protected] main-amd64-default build 2024-10-30 14:33 log report port detail FreshPorts
devel/py-pysimdjson@py311 [email protected] main-arm64-default build 2024-10-30 13:02 log report port detail FreshPorts
devel/py-pysimdjson@py311 [email protected] main-amd64-default build 2024-10-30 06:11 log report port detail FreshPorts
math/lcalc [email protected] main-i386-default build 2024-10-30 05:11 log report port detail FreshPorts
devel/py-pysimdjson@py311 [email protected] main-i386-default build 2024-10-29 21:43 log report port detail FreshPorts
lang/gnat13 [email protected] 141releng-armv7-quarterly fetch 2024-10-29 21:03 log report port detail FreshPorts
math/flexiblas [email protected] 141releng-armv7-quarterly build 2024-10-29 15:45 log report port detail FreshPorts
math/libdivide [email protected] main-amd64-default build 2024-10-29 07:23 log report port detail FreshPorts
math/libdivide [email protected] main-i386-default build 2024-10-29 05:16 log report port detail FreshPorts
devel/R-cran-rJava [email protected] 141releng-armv7-quarterly stage 2024-10-28 23:29 log report port detail FreshPorts
lang/gnat12 [email protected] 141releng-armv7-quarterly fetch 2024-10-28 16:55 log report port detail FreshPorts
math/lcalc [email protected] main-i386-default build 2024-10-27 22:14 log report port detail FreshPorts
math/libdivide [email protected] main-arm64-default build 2024-10-27 12:21 log report port detail FreshPorts
devel/py-pysimdjson@py311 [email protected] main-i386-default build 2024-10-27 09:13 log report port detail FreshPorts
math/lcalc [email protected] main-amd64-default build 2024-10-27 07:41 log report port detail FreshPorts
lang/gnat13 [email protected] 141releng-armv7-default fetch 2024-10-26 18:06 log report port detail FreshPorts
devel/py-pysimdjson@py311 [email protected] main-amd64-default build 2024-10-26 12:54 log report port detail FreshPorts
math/flexiblas [email protected] 141releng-armv7-default build 2024-10-26 12:09 log report port detail FreshPorts
math/libdivide [email protected] main-i386-default build 2024-10-26 05:52 log report port detail FreshPorts
lang/gnat12 [email protected] 141releng-armv7-default fetch 2024-10-25 11:30 log report port detail FreshPorts
math/libdivide [email protected] main-amd64-default build 2024-10-24 20:07 log report port detail FreshPorts
math/libdivide [email protected] main-i386-default build 2024-10-24 17:55 log report port detail FreshPorts
lang/gnat13 [email protected] main-armv7-default fetch 2024-10-24 07:56 log report port detail FreshPorts
math/flexiblas [email protected] main-armv7-default build 2024-10-23 22:59 log report port detail FreshPorts